1. Field of the Invention
The present invention generally relates to an input buffer, and more specifically, to an input buffer having a pull-up means.
2. Description of Related Art
Owing to the development of process technology, semiconductor devices having a power supply voltage lower than 3.3V can be achieved using deep-submicron line width technology. However, the power supply voltage of external systems that communicate with such devices commonly operate at a voltage, such as 5V, that is higher than the power supply voltage within the semiconductor device.
Thus, input circuits of the semiconductor device commonly include a high-voltage tolerant function such that device can operate stably, irrespective of the applied external voltage level.
Generally, an input circuit of the semiconductor device indicates an input buffer that buffers a signal input at a chip pad.
An input buffer having a conventional pull-up means buffers the signal input at the pad, and pulls up the pad by the pull-up means when the pad is in a floating state.
However, the input buffer having the conventional pull-up means does not pull up the pad to the power supply voltage level by the pull-up means in the case where the pad is in the floating state, and instead pulls it up to a voltage of the power supply voltage minus a threshold voltage. Accordingly, an input buffer receiving a signal from an external device connected to the pad of the semiconductor device is turned on, causing leakage current through the input buffer.
FIG. 1 is a circuit diagram of an embodiment of an input buffer having a conventional pull-up means. The pull-up means comprises an NMOS transistor N1, a PMOS transistor P1, and a buffer BUF1.
In FIG. 1, reference numeral 10 shows a pad.
The operation of the circuit illustrated in FIG. 1 is as follows.
The NMOS transistor N1 is always turned on. When a signal of a ground voltage level is applied to the pad 10, the signal of the ground voltage level is transmitted to a node n. In the case where a signal of a high voltage level, or a power supply voltage level, is applied, the voltage transmitted to node n is one of the high voltage minus the threshold voltage Vtn of the NMOS transistor N1 or the power supply voltage VDD minus the threshold voltage Vtp of the NMOS transistor N1 VDD−Vtn. That is, the NMOS transistor N1 performs a high-voltage tolerant function. The buffer BUF1 generates an input signal IN by buffering the signal applied to the node n. In such an operation, the PMOS transistor P1 is configured to not influence the voltage of the node n.
When the pad 10 is in floating state, the PMOS transistor P1 pulls up the node n to the power supply voltage VDD level. The NMOS transistor N1 transmits the voltage VDD−Vtn subtracting the threshold voltage Vtn of the NMOS transistor N1 from the power supply voltage VDD to the pad 10. That is, the pad 10 is not fully pulled up to the power supply voltage VDD level, and is pulled up to the voltage VDD−Vtn, subtracting the threshold voltage Vtn of the NMOS transistor N1 from the power supply voltage VDD. Therefore, the pad 10 is prevented from being in floating state by the PMOS transistor P1.
However, since the pad 10 is pulled up to the voltage of VDD−Vtn, subtracting the threshold voltage Vtn of the NMOS transistor N1 from the power supply voltage VDD, an input buffer connected to a pad of an external device connected to the pad 10 is turned on, causing a leakage current through the input buffer connected to the pad of the external device.
Of course, if the input buffer is configured by directly connecting the PMOS transistor P1 with the pad 10, it is possible to pull up the pad 10 to the power supply voltage level in the case where the pad 10 is in the floating state. However, in such a configuration, if a high voltage is applied to the pad 10, this configuration can cause a very large voltage difference to be applied between a gate and a drain of the PMOS transistor P1, thereby allowing for damage to the gate oxide of the PMOS transistor P1.